Storage controller and storage controller control method

ABSTRACT

A storage controller of the present invention can input and output data even when the track size, which is the host management unit, is not consistent with the block size of the storage device. A boundary correction unit adds gap data corresponding to a gap size to data in a buffer memory so that the boundary of the track and boundary of the block inside the storage device match. A guarantee code is added to each logical block received from the host, and these guarantee code-appended blocks are stored in a cache memory. By providing a gap in the storage device every 116 extended logical blocks, the start position of the lead block of a track matches up with the start position of the logical blocks of the storage device.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application relates to and claims priority from Japanese PatentApplication number 2007-303672, filed on Nov. 22, 2007, the entiredisclosure of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a storage controller and a storagecontroller control method.

2. Description of the Related Art

A storage controller, for example, is connected to a mainframe or othersuch host computer (hereinafter, “host”). The storage controllerprovides the host with a storage area based on RAID (Redundant Array ofInexpensive Disks).

In the storage controller, for example, redundancy can also be added tothe data as with the well-known RAID 1 through RAID 6. The storagecontroller prepares for a failure in a disk drive by adding parity tothe data, and writing a copy of the data to a different disk drive.

Furthermore, storage controllers that use guarantee codes are also known(Japanese Patent Laid-open No. 2000-347815, U.S. Pat. No. 5,819,054, andU.S. Pat. No. 5,706,298). In one prior art, a logical address(hereinafter, “LA (Logical Address)”) of a logical block specified asthe access destination by the host computer, and an LRC (LongitudinalRedundancy Check), which is determined by implementing an Exclusive ORoperation on the data in the logical block, are respectively added tothe logical block as a guarantee code, and this guarantee code andlogical block are saved to a disk drive.

The LA is utilized for detecting an address error in a storage area intowhich the logical block data has been written. The LRC is utilized as anerror detection symbol for detecting a data error in the logical block.

When the above-mentioned guarantee code is added to a logical block,there is a likelihood that the data management unit, which is handledinside the storage controller, will differ from the data management unitinside the disk drive. For example, in a disk drive in which the blocklength (sector length) is fixed at the size of the logical block, datais stored in logical block units. Therefore, when the block size isincreased by adding a guarantee code to the logical block, the diskdrive format may make it impossible to store the guarantee code-appendedlogical block as-is.

Accordingly, to solve for this problem, a fourth Patent Document(Japanese Patent Laid-open No. 2006-195851) proposes a technique foraffixing the lowest common multiple of the logical block size and theguarantee code-appended logical block size as a value wheninputting/outputting data to/from the disk drive.

As disclosed in the above-mentioned fourth Patent Document (JapanesePatent Laid-open No. 2006-195851), configuring the lowest commonmultiple for the logical block size and the guarantee code-appendedlogical block size as the basic unit when the storage controller iswriting data to the disk drive makes it possible to write a logicalblock, to which a guarantee code has been added, to a disk drive havinga fixed sector length. Hereinafter, a logical block whose size has beenincreased by the addition of a guarantee code will be called an extendedlogical block.

For example, if it is supposed that the size of the logical block is 512bytes and the size of the guarantee code is eight bytes, the size of theextended logical block becomes 520 bytes. The lowest common multiple of512 bytes and 520 bytes is 33280 bytes. Respectively appending 8-byteguarantee codes to each of 64 logical blocks received from the hostcomputer makes the overall data size 33280 bytes. This value correspondsto the size of 65 logical blocks (33280=512×65).

In this case, the two ends of the data configured from 64 extendedlogical blocks matches up with the two ends of the 65 logical blocks.Therefore, the 64 extended logical blocks can be stored in the diskdrive as 65 logical blocks. For convenience sake, in this specification,for example, the method for reading and writing data at the size of thelowest common multiple of the logical block size and the extendedlogical block size will be called lowest-common-multiple-unit dataaccess.

A process, which reads out old data stored in a storage device, mergesthis old data with new data, and thereafter, rewrites the merged databack to the storage device, will be called a read-modify-write process.

Now then, when the host computer is a mainframe, the mainframe managesdata in units called tracks. One track, for example, is constituted fromeither 96 or 116 logical blocks.

When a logical block targeted for updating exists in the anterior areaof a track, from the lead block to the 64^(th) logical block of thetrack, a read-modify-write process can be carried out usinglowest-common-multiple-unit data access. However, when theupdate-targeted logical block exists in the posterior area of the trackbeyond the 65^(th) logical block, using lowest-common-multiple-unit dataaccess results in processing being carried out across two tracks. Inthis case, data corresponding to the logical blocks from the 65^(th)block to the 128^(th) block must be read out from the storage device.However, the 117^(th) through the 128^(th) logical blocks constitute adifferent track.

Accordingly, when the update-targeted block location exists in the trackposterior area, it is necessary to carry out processing that spans aplurality of adjacent tracks. When a read process or a write process iscarried out for the other track adjacent to the track comprising theupdate-targeted block, it is not immediately possible to read out thedata required for updating, raising the likelihood of wait timeoccurring. The occurrence of wait time lowers the throughput of thestorage controller.

Furthermore, since a cache area for receiving the data of the adjacentother track must be secured, twice as much cache memory is needed. Thisreduces the cache hit ratio, and lowers the storage controllerthroughput.

SUMMARY OF THE INVENTION

With the foregoing in view, an object of the present invention is toprovide a storage controller and a storage controller control methodcapable of curbing performance degradation even when the size of a firstblock used in a host computer and storage device differs from the sizeof a second block used inside the storage controller. A further objectof the present invention is to provide a storage controller and storagecontroller control information capable of making the boundary of a trackconfigured from a plurality of extended logical blocks match up with theboundary of physical blocks inside a storage device. Yet further objectsof the present invention should become clear from the descriptions ofthe embodiments, which will be explained hereinbelow.

A storage controller according to a first aspect of the presentinvention designed to solve for the above-mentioned problems is astorage controller for controlling data input/output between a hostcomputer and a storage device storing the data, and comprises a firstcommunication controller, which sends/receives data to/from the hostcomputer, and which sends/receives this data to/from the host computerin first block units having a first size; a first data adder forcreating a second block having a second size that is larger than thefirst size by respectively adding a prescribed first data to each of thefirst blocks of data received from the host computer; a secondcommunication controller for sending/receiving data to/from the storagedevice, which stores the data in the first block units; a first memory,which is provided between the first communication controller and thesecond communication controller, and which manages data in the secondblock units; a second memory, which is provided between the first memoryand the storage device; and a boundary correction unit, which matchesthe boundary of a track, which is a unit of data management used by thehost computer, to the boundary of the first block inside the storagedevice, and which (1) matches the boundary of a track to the boundary ofa first block inside the storage device by adding a prescribed-sizesecond data to data to be transferred from the first memory to thesecond memory, and (2) matches the boundary of a track to the boundaryof a second block inside the first memory by removing the second datafrom the data to be transferred from the second memory to the firstmemory.

In a second aspect according to the first aspect, the boundarycorrection unit matches the start position of the lead second block ofthe respective second blocks, which configure the data to be transferredfrom the first memory to the second memory, to the start position of thefirst block inside the storage device.

In a third aspect according to either the first aspect or the secondaspect, the boundary correction unit, by adding the second data to thedata to be transferred from the first memory to the second memory, makesthis data into data that is an integral multiple of the first size.

In a fourth aspect according to any of the first through the thirdaspects, the second data is either padding data configured from a 0 bit,or indefinite data.

In a fifth aspect according to any of the first through the fourthaspects, the boundary correction unit decides the scope of the data tobe read out to the second memory from the storage device in accordancewith the location, on the track, of the second block to be updated bythe host computer.

In a sixth aspect according to any of the first through the fourthaspects, the boundary correction unit determines whether the location,on the track, of the block to be updated by the host computercorresponds to any of (C1) a first case, in which the location on thetrack is only in the track posterior area, which is subsequent to thetrack anterior area from the beginning of the track up to a data sizedetermined as the lowest common multiple of the first size and thesecond size; (C2) a second case, in which the location on the track isin both the track anterior area and the track posterior area; or (C3) athird case, in which the location on the track is only in the trackanterior area, and decides the size of data transfer between the secondmemory and the storage device in accordance with the determined case.

In a seventh aspect according to any of the first through the sixthaspects, the boundary correction unit and the second memory arerespectively disposed in the second communication controller.

In an eighth aspect according to any of the first through the sixthaspects, the boundary correction unit and the second memory arerespectively disposed in the storage device.

A storage controller control method according to a ninth aspect is amethod for controlling a storage controller, which controls datainput/output between a host computer and a storage device, andrespectively executes a step for receiving from the host computerupdate-targeted data in first block units having a first size; a stepfor respectively adding a prescribed first data to each of the firstblocks of update-targeted data, and for creating a second block having asecond size that is larger than the first size; a step for storing, in afirst memory, update-targeted data, which has been converted to data inthe second block units; a step for reading out from the storage deviceprescribed data of a prescribed scope comprising the update-targeteddata, and storing this data in a second memory; a step for removing asecond data from the prescribed data stored in the second memory,converting the prescribed data to data of an integral multiple of thesecond size, and transferring this converted data to the first memory; astep for merging in the first memory the prescribed data transferred tothe first memory with the update-targeted data stored in the firstmemory to create merged data; a step for transferring the merged data tothe second memory; a step for converting in the second memory the mergeddata to data of the integral multiple of the first size by adding aprescribed size second data at the end of the merged data; and a stepfor writing the converted merged data to the storage device.

In a tenth aspect according to the ninth aspect, (C1) in the first casewhere the location, on the track, of the update-targeted data is only inthe track posterior area, which is subsequent to the track anterior areafrom the beginning of the track up to a data size determined as thelowest common multiple of the first size and the second size, the dataof the track posterior area is read out from the storage device as thedata of the prescribed scope; (C2) in the second case where thelocation, on the track, of the update-targeted data is in both the trackanterior area and the track posterior area, the entire track is read outfrom the storage device as the data of the prescribed scope; and (C3) inthe third case where the location, on the track, of the update-targeteddata is only in the track anterior area, and the data of the trackanterior area is read out from the storage device as the data of theprescribed scope.

At least one part of either the respective units or the respective stepsof the present invention may be configured as a computer program. Thiscomputer program can be affixed to and distributed via a recordingmedium, and can also be delivered via a network.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram showing the overall concept of theembodiment of the present invention;

FIG. 2 is a block diagram showing the overall configuration of a storagesystem;

FIG. 3 is a block diagram showing the configuration of a controller;

FIG. 4 is a schematic diagram showing the relationship between a slotand a cache;

FIG. 5 is a schematic diagram showing both a table for managing thecorresponding relationship between a device ID and a VDEV, and a tablefor managing the configuration of the VDEV;

FIG. 6 is a schematic diagram showing how slots are arranged in storagedevices;

FIG. 7 is a schematic diagram showing how an extended logical block iscreated by adding a guarantee code to a logical block;

FIG. 8 is a schematic diagram showing how data stored in the storagedevice is updated on the basis of the lowest common multiple of the sizeof the logical block and the size of the extended logical block;

FIG. 9 is a schematic diagram showing how processing is carried outacross a plurality of adjacent tracks when a gap is not provided in thestorage device;

FIG. 10 is a schematic diagram showing how the starting locations at thebeginning blocks of the respective tracks are matched up to the logicalblocks inside the storage device by providing a prescribed size gap foreach prescribed number of logical blocks;

FIG. 11 is a schematic diagram showing how data is transferred from thestorage device to the cache memory by way of a buffer memory;

FIG. 12 is a schematic diagram showing how merged data in the cachememory is transferred to the buffer memory;

FIG. 13 is a schematic diagram showing how data is transferred from thebuffer memory to the storage device;

FIG. 14 is a flowchart showing a write process;

FIG. 15 is a flowchart showing a destage process in the case of RAID 1;

FIG. 16 is a flowchart showing the details of S33 of FIG. 15;

FIG. 17 is a schematic diagram showing how cases are divided inaccordance with the update location in a track, and how transferparameters are decided in accordance with the respective cases;

FIG. 18 is a flowchart showing the details of S34 of FIG. 15;

FIG. 19 is a schematic diagram showing how data on contiguous tracks istransferred from cache memory to the storage device by way of the buffermemory in a storage controller related to a second embodiment;

FIG. 20 is a schematic diagram showing how data on contiguous tracks istransferred from the storage device to the cache memory by way of thebuffer memory;

FIG. 21 is a flowchart showing a sequential read process;

FIG. 22 is a flowchart showing the details of S106 of FIG. 21;

FIG. 23 is a flowchart showing a random read process, which is executedin a storage controller related to a third embodiment;

FIG. 24 is a flowchart showing the details of S136 of FIG. 23;

FIG. 25 is a diagram schematically showing a situation in which thepresent invention is applied to RAID 5 in a storage controller relatedto a fourth embodiment; and

FIG. 26 is a block diagram showing the essential parts of a storagecontroller related to a fifth embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The embodiments of the present invention will be explained below basedon the figures. First, the concept of the present invention will beexplained initially, after which the specific embodiments will beexplained. FIG. 1 is a diagram schematically showing the concept of thepresent invention. FIG. 1 and the following disclosures related to FIG.1 present an overview of the present invention to the extent necessaryto understand and implement the present invention, and do not purport tolimit the scope of the present invention to the scope disclosed in FIG.1.

FIG. 1 (a) shows the overall configuration of a storage systemcomprising a storage controller according to the present invention. Thisstorage system, for example, comprises a storage controller 1, a storagedevice 2, and a host 3.

The storage device 2, for example, is configured as a hard disk devicein which the sector length is fixed at the size of a logical block, likea SATA (Serial AT Attachment) disk or SAS (Serial Attached SCSI) disk.Furthermore, for convenience sake, in the following explanation, aphysical block inside the storage device will be called a logical block.

However, the present invention is not limited to a SATA disk or SASdisk, and as long as the sector length of a storage device is fixed atthe logical block size, other types of storage devices, such as a flashmemory device, can also be used. Furthermore, as will become clear fromthe embodiments explained hereinbelow, it is also possible to utilize anFC disk, which can match the sector length to the size of an extendedlogical block.

The host 3 is configured as a mainframe computer. The host 3 and thestorage controller 1, for example, carry out data communications inaccordance with a communication protocol, such as FICON (FibreConnection: a registered trademark), ESCON (Enterprise SystemConnection: a registered trademark), ACONARC (Advanced ConnectionArchitecture: a registered trademark), FIBARC (Fibre ConnectionArchitecture: a registered trademark) and so forth. The host 3, forexample, can manage data in track 5 units, which are configured fromeither 96 or 116 logical blocks 6.

The storage controller 1 is disposed between the host 3 and the storagedevice 2, and controls the transfer of data between the host 3 and thestorage device 2. The storage controller 1, for example, comprises ahost communication controller 1A; a device communication controller 1B;a cache memory 1C; a guarantee code controller 1D; and a boundarycontroller 4.

This host communication controller 1A corresponds to the “firstcommunication controller”. The host communication controller 1A receivesa command and data from the host 3, and sends the result of commandprocessing to the host 3.

The device communication controller 1B corresponds to the “secondcommunication controller”. The device communication controller 1B writesdata to the storage device 2, and reads data from the storage device 2.

The cache memory 1C corresponds to the “first memory”, and stores datareceived from the host 3, and data read out from the storage device 2.

The boundary controller 4 is disposed between the cache memory 1C andthe device communication controller 1B. The boundary controller 4, forexample, comprises a buffer memory 4A; and a boundary correction unit4B.

The guarantee code controller 1D corresponds to the “first data adder”.The guarantee code controller 1D respectively adds a guarantee code 7 toeach logical block 6. The guarantee code 7 corresponds to the “firstdata”. The guarantee code 7, for example, can be configured from alogical address (LA) and a LRC.

The buffer memory 4A corresponds to the “second memory”. The buffermemory 4A is disposed between the cache memory 1C and the devicecommunication controller 1B. The cache memory 1C and storage device 2send and receive data via the buffer memory 4A.

The boundary correction unit 4B corresponds to the “boundary correctionunit”. The boundary correction unit 4B, as will be explained below usingFIG. 1 (b), adds gap data corresponding to a gap size δ so that thetrack 5 boundary matches up with the boundary of a block 6 inside thestorage device 2. The gap data corresponds to the “second data”.

FIG. 1 (b) shows a processing method for making the track 5 boundarymatch the boundary of a block 6 inside the storage device 2. The host 3manages data in track units, and the respective tracks 5, for example,are configured from either 96 or 116 logical blocks 6. Hereinafter, asituation in which a single track 5 is configured from 116 logicalblocks 6 will be given as an example and explained.

The size DL6 of a logical block 6, for example, is 512 bytes. Thislogical block 6 corresponds to the “first block”. The guarantee codecontroller 1D adds a guarantee code 7 to the logical block 6. The sizeDL7 of the guarantee code 7, for example, is eight bytes.

Adding an 8-byte guarantee code 7 to a 512-byte logical block 6 createsan extended logical block 8. The extended logical block 8 corresponds tothe “second block”. The size DL8 of the extended logical block 8 is 520bytes (DL8=DL6+DL7=512+8).

A guarantee code 7 is added to each logical block 6 received from thehost 3, and these extended logical blocks 8 are stored in the cachememory 1C. The top portion of FIG. 1 (b) shows the state inside thecache memory 1C, and the bottom portion of FIG. 1 (b) shows the stateinside the storage device 2.

Since the size of an extended logical block 8 stored in the cache memory1C differs from the size of a logical block 6 stored in the storagedevice 2, the boundary B2 of an extended logical block 8 does not matchup with the boundary B1 of a logical block 6.

However, when the size of the data stored in the cache memory 1C and thesize of the data stored in the storage device 2 constitute the valueDL5A (LCM) of the lowest common multiple of the size DL6 of the logicalblock 6 and the size DL8 of the extended logical block 8, the twoboundaries B3 and B2 match. More specifically, the one data size, whichcomprises 64 extended logical blocks 8, matches the other data size,which comprises 65 logical blocks 6. Therefore, the boundaries at thetwo ends of the one data size match up with the boundaries at the twoends of the other data size.

As shown in the upper left portion of FIG. 1 (b), a certain track 5 isconfigured from a total of 116 extended logical blocks 8 from the 0^(th)to the 115^(th) block. As shown by the dark box, a situation in whichthe host 3 has issued an update request for the 114^(th) block 8 will beconsidered.

In order to process the update request, the storage controller 1 mustread the old data out from the storage device 2, and merge new data withthe old data. For this reason, if the 64^(th) extended logical block 8is the lead block, and data corresponding to 64^(th) extended logicalblocks 8 is read out from the storage device 2, data up to the block 6corresponding to the adjacent track (the track configured from the116^(th) and subsequent extended logical blocks 8) will be read out.

That is, a total of 65 logical blocks 6, from the 65^(th) logical block6 to the 129^(th) logical block 6, are read out from the storage device2. However, logical blocks, which store only data related to theadjacent track 5, are included among these 65 logical blocks 6.Therefore, if the host 3 is accessing the adjacent track 5, the updaterequest related to the 114^(th) extended logical block 8 cannot beprocessed until this access ends.

Accordingly, in this embodiment, providing a gap δ in the storage device2 every 116 extended logical blocks causes the start location of thelead block of a track 5 to match up with the start location of thelogical blocks 6 of the storage device 2. That is, in this embodiment,adding size δ worth of gap data at the end of each track causes the leadlocations of the respective tracks to match up with the boundaries B1 ofthe logical blocks 6.

As described hereinabove, in this embodiment, a gap δ of a prescribedsize (in this case, 96 bytes) is created in the storage device 2 betweenthe end B3 of the previous track 5 and the start B3 of the adjacenttrack 5.

The storage controller 1 reads out from the storage device 2 a total of53 logical blocks 6 of data, from the 65^(th) logical block 6 to the117^(th) logical block 6, and stores these blocks 6 in the buffer memory4A. The data transferred from the storage device 2 to the buffer memory4A comprises the above-mentioned gap data.

The boundary correction unit 4B transfers to the cache memory 1C onlythe part of the data stored in the buffer memory 4A from which the gapdata has been removed. Removing the gap data makes this data the size ofthe integral multiple of the size DL8 of the extended logical block 8.That is, the data from the 64^(th) extended logical block 8 to the115^(th) extended logical block 8 is stored in the cache memory 1C.

As described hereinabove, since the gap data is not transferred from thebuffer memory 4A to the cache memory 1C, command processing is notimpacted at all no matter what kind of data is stored in the gap δ inthe storage device 2.

The storage controller 1 merges the old data related to the 64^(th)through the 115^(th) extended logical blocks 8 transferred from thebuffer memory 4A to the cache memory 1C with the new data related to the114^(th) extended logical block 8 received from the host 3 in the cachememory 1C.

The merged data is transferred from the cache memory 1C to the buffermemory 4A. The boundary correction unit 4B adds gap data at the end ofthe merged data in the buffer memory 4A. Consequently, the merged databecomes data having the size of the integral multiple of the logicalblock 6 size DL6. The gap data-appended merged data is stored in the65^(th) through the 117^(th) logical blocks 6.

The above explanation explains a situation in which the location of theextended logical block 8 updated by the host 3 exists in the posteriorarea of the track 5. In this embodiment, the size of the datatransferred between the buffer memory 4A and cache memory 1C iscontrolled by the location of the block to be updated.

A track 5 can be broadly divided into an anterior area DL5A and aposterior area DL5B. The anterior area DL5A corresponds to the “trackanterior area”, and the posterior area DL5B corresponds to the “trackposterior area”.

For example, the anterior area DL5A can be defined as an area of a sizethat enables data access in a lowest common multiple unit from thebeginning of the track 5. The posterior area DL5B can be defined as anarea from the end of the anterior area DL5A to the end of the track 5.

When a block targeted for update by the host 3 is located in theanterior area DL5A, since data access can be carried out in a lowestcommon multiple (L.C.M.) unit, 65 logical blocks 6 can be read out fromthe storage device 2. Since both ends of the anterior area DL5A matchthe boundaries of the logical blocks 6 of the storage device 2, there isno need to add gap data.

By contrast, when the block targeted for update by the host 3 is locatedin the posterior area DL5B, data access cannot be carried out using alowest common multiple unit. This is because the track size DL5subsequent to adding a guarantee code 7 is not an integral multiple ofthe value of the lowest common multiple of the logical block 6 size andthe extended logical block 8 size. Therefore, when updating a blocklocated in the posterior area DL5B, as described hereinabove, gap datais appended at the end of the extended logical block 8 belonging to theposterior area DL5B, and this gap data-appended extended logical block 8is written to the storage device 2.

When blocks targeted for updating by the host 3 are located in both theanterior area DL5A and posterior area DL5B, adding the gap data makes itpossible to carry out a read-modify-write process in track units.

Configuring this embodiment like this enables a guarantee code7-appended extended logical block 8 to be stored in a storage device 2having a fixed block size of 512 bytes.

Furthermore, in this embodiment, since the lowest common multiple of thelogical block 6 size and the extended logical block 8 size does notmatch the track size, which is the management unit of the host 3, awrite process can be carried out using only the data corresponding tothe track having the update-targeted block, and there is no need tocarry out write processing across a plurality of adjacent tracks.Therefore, in this embodiment, it is not necessary to wait until commandprocessing related to an adjacent track ends. Furthermore, in thisembodiment, it is possible to prevent increased utilization of the cachememory 1C, and to curb a drop in the cache hit ratio. Eliminating waittime and preventing a drop in the cache hit ratio can prevent thedegradation of storage controller 1 throughput. This embodiment will beexplained in detail below.

Embodiment 1

FIG. 2 is a schematic diagram showing the overall configuration of astorage system comprising a storage controller 10 related to thisembodiment. This storage system, for example, can comprise at least onestorage controller 10; either one or a plurality of hosts 20; and atleast one management terminal 30.

The corresponding relationship to this embodiment described hereinaboveusing FIG. 1 will be explained. The storage controller 10 corresponds tothe storage controller 1 of FIG. 1; storage device 210 correspond to thestorage device 2 of FIG. 1; host 20 corresponds to the host 3 of FIG. 1;channel adapter 110 corresponds to the host communication controller 1Aof FIG. 1; disk adapter 120 corresponds to device communicationcontroller 1B of FIG. 1; and cache memory 130 corresponds to the cachememory 1C of FIG. 1.

Guarantee code circuit 112A shown in FIG. 3 corresponds to the guaranteecode controller 1D of FIG. 1; DMA circuit 122 shown in FIG. 3corresponds to the boundary controller 4 of FIG. 1; and buffer memory122A shown in FIG. 3 corresponds to the buffer memory 4A of FIG. 1. Theboundary correction unit 4B of FIG. 1 is realized by a processor insidethe DMA circuit 122 executing a microprogram stored in the memory insidethe DMA circuit 122. The boundary correction method will be explainedhereinbelow using another figure.

The host 20 and management terminal 30 will be explained first, and thestorage controller 10 will be explained next. The host 20, for example,is configured as a mainframe computer, and is connected to the storagecontroller 10 via a communications network CN1. The communicationnetwork CN1, for example, can be configured as an FC-SAN (FibreChannel-Storage Area Network) or other such communication network.

The host 20, for example, uses a track configured from either 96 or 116logical blocks as a unit for managing data. Furthermore, the presentinvention is applicable if the computer manages data in a size that isnot the integral multiple of the lowest common multiple of the logicalblock size and extended logical block size. The host 20 issues a readcommand or a write command to the storage controller 10, and receivesthe result of this processing from the storage controller 10.

The management terminal 30 is connected to a service processor 160inside the storage controller 10 via a communication network CN3. Thecommunication network CN3, for example, is configured as a communicationnetwork such as a LAN (Local Area Network). The management terminal 30collects various types of information inside the storage controller 10via the service processor (hereinafter, SVP) 160. The managementterminal 30 can specify various configurations inside the storagecontroller 10 via the SVP 160.

The configuration of the storage controller 10 will be explained. Thestorage controller 10 can be broadly divided into a controller 100; anda storage device installation unit 200. The controller 100, for example,comprises at least one or more channel adapters (hereinafter, CHA) 110;at least one or more disk adapters (hereinafter, DKA) 120; at least oneor more cache memories 130; at least one or more shared memories 140; aconnector (“SW” in the figure) 150; and an SVP 160. Furthermore, theconfiguration can be such that a plurality of controllers 100 is linkedtogether via a switch. For example, a plurality of controllers 100 canalso be configured into a cluster.

The CHA 110 is for controlling data communications with the host 20,and, for example, is configured as a computer device comprising amicroprocessor and a local memory. Each CHA 110 comprises at least oneor more communication ports.

The DKA 120 is for controlling data communications with the respectivestorage devices 210, and like the CHA 110, is configured as a computerdevice comprising a microprocessor and local memory.

The respective DKA 120 and the respective storage devices 210, forexample, are connected by way of a communication network CN2, whichconforms to a fibre channel protocol. The respective DKA 120 and therespective storage devices 210 transfer data in block units.

The path, by which the controller 100 accesses the respective storagedevices 210, is made redundant. If a failure occurs in any one of theDKA 120 or communication networks CN2, the controller 100 can access astorage device 210 using the other DKA 120 and communication networkCN2. Similarly, the path between the host 20 and the controller 100 canalso be made redundant. The configurations of the CHA 110 and DKA 120will be explained hereinbelow using FIG. 3.

The operations of the CHA 110 and DKA 120 will be briefly explained. TheCHA 110, upon receiving a read command issued from the host 20, storesthis read command in the shared memory 140. The DKA 120 constantlyreferences the shared memory 140, and upon detecting an unprocessed readcommand, reads out the data from the storage device 210, and stores thisdata in the cache memory 130. The CHA 110 reads out the data transferredto the cache memory 130, and sends this data to the host 20.

Conversely, when the CHA 110 receives a write command issued from thehost 20, the CHA 110 stores this write command in the shared memory 140.The CHA 110 stores the received write-data in the cache memory 130.Subsequent to storing the write-data in the cache memory 130, the CHA110 notifies the host 20 that the write has ended. The DKA 120 reads outthe data stored in the cache memory 130 in accordance with the writecommand stored in the shared memory 140, and stores this data in theprescribed storage device 210.

The cache memory 130, for example, is for storing user data and the likereceived from the host 20. The cache memory 130, for example, isconfigured from either a volatile memory or a nonvolatile memory. Theshared memory 140, for example, is configured from a nonvolatile memory.The shared memory 140 stores a variety of tables T and managementinformation, which will be explained hereinbelow.

The cache memory 130 and the shared memory 140 can be coexistentlyprovided on the same memory board. Or, one part of the memory can beused as the cache area, and the other part can be used as the controlarea.

The connector 150 respectively connects the respective CHA 110,respective DKA 120, cache memory 130, and shared memory 140.Consequently, the CHA 110, DKA 120, cache memory 130, and shared memory140 are all accessible to one another. The connector 150, for example,can be configured as a crossbar switch or the like.

The SVP 160 is respectively connected to the respective CHA 110 andrespective DKA 120 via a LAN or other such internal network CN4.Further, the SVP 160 is connected to the management terminal 30 via thecommunication network CN3. The SVP 160 collects various statuses insidethe storage controller 10, and provides these statuses to the managementterminal 30. Furthermore, the SVP 160 can also be connected to only oneof either the CHA 110 or DKA 120. This is because the SVP 160 is able tocollect the various status information via the shared memory 140.

The controller 100 configuration is not limited to the above-describedconfiguration. For example, the configuration can be such that thefunction for carrying out data communications with the host 20, thefunction for carrying out data communications with the storage devices210, the function for temporarily storing data, and the function forrewritably storing various types of tables are respectively provided onone or a plurality of control boards.

The configuration of the storage device installation unit 200 will beexplained. The storage device installation unit 200 comprises aplurality of storage devices 210. The respective storage devices 210,for example, are configured as hard disk devices. Flash memory devices,magneto-optical storage devices, and holographic memory devices can beutilized instead of hard disk devices.

Although the grouping will differ according to the RAID configuration,for example, a parity group 220 is configured in accordance with aprescribed number of storage devices 210, such as a two-device group ora four-device group. The parity group 220 is the virtualization of thephysical storage areas possessed by the respective storage devices 210inside the parity group 220.

Therefore, the parity group 220 is a virtualized physical storage device(VDEV). Either one or a plurality of logical devices (LDEV) 230 can beconfigured in the physical storage area of the parity group 220. Alogical device 230 is mapped to a LUN (Logical Unit Number) and providedto the host 20.

In this embodiment, the storage device 210 will be explained using theexample of a hard disk device. However, as mentioned above, the presentinvention is also capable of using storage devices other than hard diskdevices. Further, for ease of understanding, a storage device will beexpressed as a “disk” in the flowcharts.

FIG. 3 is a block diagram showing the configurations of the CHA 110 andDKA 120. The CHA 110, for example, comprises a protocol chip 111; a DMAcircuit 112; and a microprocessor 113. The protocol chip 111 is acircuit for carrying out communications with the host 20. Themicroprocessor 113 controls the overall operation of the CHA 110.

The DMA circuit 112 is a circuit for transferring data between theprotocol chip 111 and the cache memory 130 using the DMA (Direct MemoryAccess) mode. The DMA circuit 112 comprises a guarantee code circuit112A. The guarantee code circuit 112A creates an extended logical blockby configuring a guarantee code in a logical block received from thehost 20. Furthermore, the guarantee code circuit 112A restores thelogical block by removing the guarantee code from the extended logicalblock read into the cache memory 130.

The DKA 120, like the CHA 110, for example, comprises a protocol chip121; a DMA circuit 122; and a microprocessor 123. Furthermore, the DKA120 can also comprise a parity creation circuit 124.

The protocol chip 121 is a circuit for communicating with the respectivestorage devices 210. The microprocessor 123 controls the overalloperation of the DKA 120. The parity creation circuit 124 is a circuitfor creating parity data by carrying out a prescribed logical operationbased on data stored in the cache memory 130.

The DMA circuit 122 is for carrying out the transfer of data between thestorage device 210 and the cache memory 130 using the DMA mode. The DMAcircuit 122 comprises a buffer memory (hereinafter, also called thebuffer) 122A, and executes a DMA transfer via this buffer memory 122A.That is, data is sent and received between the cache memory 130 and thestorage device 210 by way of the buffer memory 122A. As will beexplained hereinbelow, the data boundary is adjusted in the buffermemory 122A.

FIG. 4 is a diagram schematically showing the management method of thecache memory 130. As shown in the top portion of FIG. 4, data sent fromthe host 20 to the storage controller 10 can be partitioned into eitherone or a plurality of slots.

Data, which is received from the host 20 and divided into a prescribednumber of blocks, is called a slot 300. In the case of a mainframe,there is a track, which is a management unit peculiar to the mainframe,and the track is configured from either 96 or 116 logical blocks 301.The size of one logical block 301, for example, is 512 bytes.

In the case of a mainframe, the slot size matches the track size. Thisis because matching the slot size to the track size makes it easier forthe mainframe to carry out processing for issuing a command byspecifying a track number. Therefore, in this embodiment, the slot shownin FIG. 4 can be thought of as a track.

The cache memory 130 is configured from a plurality of segments 131. Thesize of one segment 131, for example, is 64 KB. Data from the host 20 isstored in a segment 131, which is allocated in slot units.

A slot management table T10 manages the corresponding relationshipbetween a slot 300 and a segment 131 (hereinafter, the slot managementtable T10 will also be called the SLCB). The slot management table T10,for example, correspondently manages a slot number; VDEV number; segmentaddress; dirty-bitmap; and slot status.

The slot number is identification information for specifying a slot 300that is being targeted. The VDEV number is identification informationfor specifying the VDEV 220 mapped to the targeted slot 300. The segmentaddress is information for identifying the segment to which thisspecified slot is to be allocated. That is, the segment address showsthe storage-destination address of the data in this slot. When a segmentis not allocated to a slot, “0” is configured as the value of thesegment address.

The dirty-bitmap is update location management information forspecifying an update location inside the relevant slot 300. One bit isrespectively allocated to each logical block configuring a slot. A “1”is configured in an updated logical block, and a “0” is configured in alogical block that has not been updated. Therefore, referencing thedirty-bitmap makes it possible to learn which logical blocks in the slotare update-targeted logical blocks.

The slot status is information showing the status of the relevant slot.The status can be given as dirty, clean, or free. Dirty shows a state inwhich one or more “1” values are configured in the dirty-bitmap. Thatis, a dirty state shows a slot comprising an update-targeted logicalblock. Clean shows a state in which update-targeted data inside the slothas been written to the storage device 210, and the destage process hasended. Free shows a state in which the segment allocated to the relevantslot has been freed up and can be allocated to another slot.

Using the slot management table T10 can make it easy to manage the areaof cache memory 130 in which data received from the host 20 is stored,the presence or absence of update data, and the location of update data.

FIG. 5 is a schematic diagram respectively showing a device ID-VDEVcorrespondence management table T20 and VDEV management table T30. Theserespective tables T20, T30 are stored in the shared memory 140. The CHA110 and DKA 120 can copy at least a portion of the respective tablesT20, T30 to the memories inside the CHA 110 and DKA 120, and can makeuse of this information.

The device ID-VDEV correspondence management table T20 is for managingthe corresponding relationship between a logical device 230 and avirtual intermediate device VDEV 220. This table T20 correspondentlymanages a device ID_C21; and a VDEV number C22. The device ID_C21 isinformation for identifying a logical device 230. The VDEV number C22 isinformation for identifying a VDEV 220.

The VDEV management table T30 is for managing the configurations of therespective VDEV. The VDEV management table T30, for example,correspondently manages the VDEV number C31; slot size C32; RAID levelC33; number of data drives C34; number of slots in the parity cycle C35;and disk type C36.

The VDEV number C31 is information for identifying the respective VDEV220. The slot size C32 shows the number of logical blocks configuringthe slot mapped to the relevant VDEV. The RAID level C33 shows the RAIDtype, such as RAID 1 through RAID 6. The number of data drives C34 showsthe number of storage devices that store data.

The number of slots in the parity cycle C35 shows the number of slotsincluded in one parity cycle. The disk type C36 shows the type ofstorage device 210 configuring the relevant VDEV 220.

FIG. 6 is a diagram schematically showing the mapping status between aslot 300 and a storage device 210. FIG. 6 (a) shows the situation forRAID 5, and FIG. 6 (b) shows the situation for RAID 1.

FIG. 6 (a) shows a 3D+1P RAID 5 configured from three data disks (#0,#1, #2) and one parity disk (#3). Slot #0 through slot #7 are arrangedin data disk (#0), slot #8 through slot #15 are arranged in data disk(#1), slot #16 through slot #23 are arranged in data disk (#2), andparity #0 through parity #7 are arranged in the parity disk (#3) on theright side. That is, eight contiguous slots are respectively arranged ineach data disk.

An 8-slot parity (#0 through #7) size is called a parity cycle. In theparity cycle subsequent to the parity cycle shown in the figure, parityis stored in disk (#2), which is adjacent to disk (#3) on the left.Furthermore, in the subsequent parity cycle, parity is stored in disk(#1). Thus, the disk, in which parity data is stored, moves each paritycycle. As is clear from FIG. 6 (a), the number of slots included in oneparity cycle (C35 in table T30) is determined by multiplying the numberof data disks by eight.

FIG. 6 (b) shows a RAID 1 configuration. In RAID 1, the same data isrespectively stored in both a primary disk and a secondary disk. Thenumber of slots included in the parity cycle for RAID 1 is eight.

As described hereinabove, the mapping status of a slot and a storagedevice can be determined from the RAID level (C33) and the number ofdata drives (C34). Therefore, the storage destination for data receivedfrom the host 20 can be computed based on the above-mentioned mappingstatus.

FIG. 7 is a schematic diagram showing the relationship between a logicalblock and an extended logical block. As shown in FIG. 7 (a), a logicalblock 301 has a size of 512 bytes. The host 20 and storage device 210use the logical block 301 as the minimal management unit.

As shown in FIG. 7 (b), the CHA 110 respectively adds an 8-byteguarantee code 310 to each logical block 301 for data received from thehost 20. The guarantee code 310, for example, comprises an LA and LRC.Adding an 8-byte guarantee code 310 to a 512-byte logical block 301creates an extended logical block 320. The extended logical block 320 isstored in the cache memory 130. When data is sent to the host 20 fromthe CHA 110, the guarantee code 310 is removed from the extended logicalblock 320, and this data is sent to the host 20 as a logical block 301.

As shown in FIG. 7 (c), for a storage device 210 configurable in aformat of 520-byte units, like an FC disk, the extended logical block320 can be stored as-is.

FIG. 8 is a diagram schematically showing how to store data of extendedlogical blocks 320 in a disk having a fixed sector length of 512 bytes,like a SAS disk or SATA disk.

As shown in FIG. 8 (a), an extended logical block 320 is created byadding a guarantee code 310 to each logical block 301 of data receivedfrom the host 20. Data converted to the extended logical block format isstored in the cache memory 130.

As shown in FIG. 8 (b), a storage device 210 like a SAS disk or SATAdisk reads and writes data in units of 512 bytes. Therefore, a 520-byteextended logical block 320 cannot be written as-is to the storagedevice.

Accordingly, the lowest common multiple (33280 bytes) of the size of alogical block 301 (512 bytes) and the size of an extended logical block320 (520 bytes) is made the data input/output size to the storage device210. The total size of 64 extended logical blocks 320 (64×520=33280)matches the total size of 65 logical blocks 301 (65×512=33280).Therefore, 64 extended logical blocks 320 can be written to the storagedevice 210 and read out from the storage device 210 as one unit.

Premised on the above, a read-modify-write process, which makes use ofdata access that uses the lowest common multiple unit, will beexplained. When a logical block comprising updated data (NEW) isreceived from the host 20 as shown in FIG. 8 (c), the CHA 110 creates anextended logical block 320 by adding a guarantee code 310 to theupdated-data logical block 301 as shown in FIG. 8 (d). Hereinafter, anupdate-targeted block may be called an update block.

As shown in FIG. 8 (e), the DKA 120 reads out the old data (OLD) fromthe storage device 210, and stores this data in the cache memory 130. Asdescribed hereinabove, the data comprising 65 logical blocks isequivalent to the data comprising 64 extended logical blocks. Therefore,the DKA 120 can obtain 64 extended logical blocks worth of data byreading out 65 contiguous logical blocks 301 from the storage device210.

As shown in FIG. 8 (f), new data is placed in the update-targetedextended logical block 320 in the cache memory 130. Thereafter, as shownin FIG. 8 (g), the 64 extended logical blocks 320 into which the newdata has been stored, are written to the storage device 210 as 65logical blocks 301.

In RAID 1, the logical block 320 into which the old data has beenwritten is simply rewritten to the logical block 320 in which the newdata is stored. When using parity as in RAID 5, a new parity is createdfrom the old data, new data and old parity. The parity is written to thestorage device 210 in a unit of 64 extended logical blocks the same asthe data.

FIG. 9 is a schematic diagram showing a situation in which the size ofthe track, which is the basic management unit of the host 20, is notconsistent with the lowest common multiple of the logical block size andthe extended logical block size. The host 20 can update data in alogical block 301 unit, but the basic unit for managing data in the host20 is the track. One track is configured from either 96 or 116 logicalblocks 301. An example, in which a track is configured from 116 logicalblocks and the 114^(th) block is to be updated, will be given in theexplanation.

As shown in FIG. 9 (a), the cache memory 130 stores data in the extendedlogical block 320 format. The number of blocks will remain the same at116, but the data size will increase due to the addition of guaranteecodes 310.

To carry out a read-modify-write process, the old data of theupdate-targeted block must be read out from the cache memory 130. Asituation, in which 65 logical blocks 301, which comprise the old data,are read out from the storage device 210 usinglowest-common-multiple-unit data access, will be considered.

As shown in FIG. 9 (b), to read out the old data, the logical blocks 301from the 65^(th) through the 129^(th) blocks are read out from thestorage device 210. However, the 117^(th) through the 129^(th) logicalblocks 301 are mapped to track #1. That is, the boundary between track#0, in which the update-targeted logical block 301 (#114) exists, andtrack #1, which is adjacent to this track #0, does not match up with theboundary of the logical block 301 inside the storage device 210.

Therefore, reading out the data, which exists in the posterior area oftrack #0 (64^(th) through the 115^(th) extended logical blocks 320) fromthe storage device 210 using lowest-common-multiple-unit data accesswill involve carrying out processing that spans the two adjacent tracks#0 and #1.

FIG. 10 shows a method for accessing the storage device 210 inaccordance with this embodiment. In this embodiment, the start locationsof the lead blocks of the respective tracks are matched up with thestart locations of the logical blocks inside the storage device 210 bydisposing a gap δ of a prescribed size in the storage device 210 every116 logical blocks. In the example shown in FIG. 10, the size of the gapδ is 96 bytes.

A read-modify-write process according to this embodiment will beexplained by referring to FIGS. 11 through 13. Hereinafter, theexplanation will focus mainly on RAID 1.

As shown in FIG. 11 (1), when updating the 114^(th) extended logicalblock 320 of track #0, the data of the posterior area (BAS 2) is readout from the storage device 210, and stored in the buffer memory 122A.In FIG. 11 (1), size δ gap data 340 is stored at the end of the datashown using diagonal lines.

As shown in FIG. 11 (2), the DKA 120 transfers to the cache memory 130only those parts of the data from which the old data, which correspondsto the update-targeted data, and the gap data 340 have been removed fromthe data stored in the buffer memory 122A. In (b) of FIG. 11 (2), thescope of the data that is not transferred from the buffer memory 122A tothe cache memory 130 is shown using dotted lines.

As shown in FIG. 12 (3), the update-targeted data (data of extendedlogical block #114) and the data read out from the storage device 210are merged together inside the cache memory 130.

As shown in FIG. 12 (4), the post-merge data is transferred from thecache memory 130 to the buffer memory 122A.

As shown in FIG. 13 (5), a gap δ worth of data 340 is added at the endof the post-merge data in the buffer memory 122A. That is, gap data 340is added such that the boundary of the post-merge data (the boundary inthe right side of the figure) matches the end location of the logicalblock 301.

As shown in FIG. 13 (6), the data added in the gap data 340 istransferred to the storage device 210 from the buffer memory 122A, andwritten into the respective logical blocks 301 (#65 through #117) of thestorage device 210.

As described hereinabove, in this embodiment, gap data 340 is added inthe buffer memory 122A such that the end of the track matches up withthe boundary of the logical block 301 inside the storage device 210.

When the data is read out from the storage device 210, as describedusing FIG. 11 (1), the gap data 340 is also transferred to the buffermemory 122A. However, as described using FIG. 11 (2), the gap data 340remains in the buffer memory 122A and is not transferred to the cachememory 130. Since the gap data 340 is not transferred to the cachememory 130, this gap data 340 is not used by the host 20. Therefore, allthe values of the gap data 340 can be “0” and there is no need tostipulate a particular value.

The operation of this embodiment will be explained based on FIGS. 14through 18. FIG. 14 is a flowchart showing a write command process. Thisprocess is executed by the CHA 110.

The CHA 110, upon receiving a write command from the host 20 (S10),converts the write-start address to a combination of the VDEV number andslot number (S11). The write command specifies the logical device ID,write-start address, and write-size. Therefore, the CHA 110 specifiesthe write-targeted VDEV number by referencing the device ID-VDEVcorrespondence management table T20 based on the specified device ID.Furthermore, the CHA 110 can detect the write-targeted slot number byreferencing the VDEV management table T30 based on the specified VDEVnumber.

The CHA 110 computes the transfer-end slot number (S12). Thetransfer-end slot number is the final slot number of the write-data. TheCHA 110 can determine the final slot number of this write-data bydividing a value arrived at by adding the write-size to the write-startaddress by the slot size.

The CHA 110 determines whether or not a SLCB mapped to thewrite-targeted slot already exists (S13). That is, the CHA 110determines whether or not a cache memory 130 segment 131 has beenallocated to the write-targeted slot (S13).

When a SLCB has not yet been allocated to the write-targeted slot (S13:NO), the CHA 110 allocates one SLCB to this write-targeted slot (S14).The CHA 110 configures the address of a free segment 131 in thisallocated SLCB (S15). Consequently, the write-targeted slot is mapped tothe segment 131, and preparations are complete for storing the data ofthe write-targeted slot in the cache memory 130.

When a SLCB has already been allocated to the write-targeted slot (S13:YES), S14 and S15 are skipped, and processing moves to S16.

The CHA 110 configures the slot status of the write-targeted slot todirty prior to receiving the write-data (S16). Next, the CHA 110transfers the write-data (the data for the write-targeted slot) receivedfrom the host 20 to the segment address allocated to the write-targetedslot (S17). Consequently, the write-data received from the host 20 isstored in the prescribed segment inside the cache memory 130.

Furthermore, when the write-data received from the host 20 istransferred to and stored in the prescribed segment inside the cachememory 130, a guarantee code 310 is respectively added to each logicalblock 301 in this write-data. Therefore, the write-data is stored in thecache memory 130 in the extended logical block 320 format.

The CHA 110 configures the dirty-bitmap to ON (“1”) for the logicalblock 301 updated by the write-data (S18). Consequently, it is possibleto manage the logical block 301 inside this write-targeted slot in whichthe updated data is stored.

The CHA 110 determines whether or not the number of the slot targeted inthis process matches the transfer-end slot number determined in S12(S19). When the process-targeted slot number and the transfer-end slotnumber do not match (S19: NO), the CHA 110 increments by one theprocess-targeted slot number (S20), and returns to S13. When both slotnumbers are a match (S19: YES), this processing ends.

When the host 20 writes write-data to a plurality of contiguous slots,that is, when the host 20 carries out a sequential write, S13 throughS19 are executed repeatedly in accordance with the number of slots. Whenthe host 20 updates either one or a plurality of logical blocks 301inside one slot, S13 through S19 are executed only once each.

A destage process will be explained based on FIG. 15. The destageprocess is for writing the data in the cache memory 130 to the storagedevice 210. The destage process is executed by the DKA 120.

In the destage process, as described using FIGS. 11 through 13, the olddata in the update-targeted track (update-targeted slot) is read out(FIG. 11), the update data received from the host 20 is merged with theold data (FIG. 12), and this merged data is written to the storagedevice 210 (FIG. 13).

The buffer memory 122A is used to transfer the data between the cachememory 130 and the storage device 210. A boundary correction process isimplemented in this buffer memory 122A to make the data boundariesuniform. Therefore, the boundary correction process is executed bothwhen the old data is transferred from the storage device 210 to thecache memory 130 (first boundary correction process), and when themerged data is transferred from the cache memory 130 to the storagedevice 210 (second boundary correction process).

Furthermore, when all the blocks of the update-targeted track are to beupdated, there is no need to read out the old data from the storagedevice 210. The example used in the explanation here is of a situationin which a number of blocks inside the track are updated.

The DKA 120 accesses the SLCB inside the shared memory 140, and checkswhether or not there is an SLCB in which the slot status is configuredas dirty. If the DKA 120 detects an SLCB in which the slot status hasbeen configured as dirty (S30), the DKA 120 acquires the slot number andVDEV number from this SLCB (S31).

On the basis of the VDEV number, the DKA 120 references the VDEVmanagement table T30 and acquires the disk type of this VDEV. The DKA120 determines whether or not this disk type is an FC disk (S32).

When the disk type is not FC disk (S32: NO), the size of the extendedlogical block 320 inside the cache memory 130 will not match the size ofthe logical block 301 inside the storage device 210.

Accordingly, the DKA 120 executes the first boundary correction processto make the boundary of the old data read out from the storage device210 match up with the boundary of the extended logical block 320 insidethe cache memory 130 (S33). This first boundary correction process willbe explained in detail hereinbelow using FIG. 16.

Subsequent to the end of the first boundary correction process, the DKA120 carries out a destage process for both the primary disk (primarystorage device) and secondary disk (secondary storage device) (S34). Inthis destage process, data is written from the cache memory 130 to thestorage device 210 by way of the buffer memory 122A. The second boundarycorrection process is executed when the data is transferred from thebuffer memory 122A to the storage device 210. The destage process (S34)will be explained in detail hereinbelow using FIG. 18.

Now then, when the disk type is FC disk (S32: YES), the DKA 120 executesa destage process for the FC disk (S35). As described in FIG. 7, thesector length of the FC disk can be configured to 520 bytes.

Therefore, the size of the extended logical block 320, which is the datamanagement unit inside the cache memory 130, matches the datainput/output unit of the FC disk 210. For this reason, data can betransferred between the FC disk and the cache memory 130 withoutcarrying out a boundary correction process. Therefore, furtherexplanation of the FC disk destage process will be omitted.

Furthermore, in a different embodiment, which will be explainedhereinbelow, carrying out a boundary correction process inside thestorage device 210 enables a disk other than a FC disk (such as a SASdisk or SATA disk) to be used the same as an FC disk.

FIG. 16 is a flowchart showing the details of the boundary correctionprocess presented in S33 of FIG. 15. This boundary correction processcorrects the data boundaries when data is transferred from the storagedevice 210 to the cache memory 130.

The DKA 120 checks the number of logical blocks configuring the slot(S50), and determines if the number of logical blocks configuring oneslot is either 96 block or 116 blocks (S51).

As mentioned hereinabove, in a mainframe, one slot (a track) isconfigured from either 96 or 116 logical blocks. In the case of an opensystem host, one slot is configured from either 128 or 512 logicalblocks.

When the number of logical blocks per slot is neither 96 nor 116 blocks(S51: NO), the DKA 120 configures a DMA 122 transfer parameter on thebasis of the lowest common multiple of the size of the logical block 301and the size of the extended logical block 320 (S52). That is, the DKA120 transfers the data from the storage device 210 to the cache memory130 by treating 65 logical blocks 301 as one unit (S58).

When the number of logical blocks per slot is either 96 or 116 (S51:YES), the DKA 120 references the SLCB of the transfer-targeted slot, andchecks the status of the dirty-bitmap configured in this SLCB (S53).

On the basis of the dirty-bitmap status, the DKA 120 determines if adata transfer from the storage device 210 to the cache memory 130corresponds to any of a plurality of preconfigured cases (S54).

Refer to FIG. 17. FIG. 17 is a schematic diagram showing how a DMA 122transfer parameter is configured in accordance with a case. FIG. 17 (a)shows a plurality of cases classified in accordance with the location ofthe update-targeted block.

As described hereinabove, a track can be broadly divided into ananterior area (BAS1) data-accessible using a lowest-common-multipleunit, and a posterior area (BAS2), which follows after the anteriorarea. Accordingly, in this embodiment, a DMA transfer is handled bydividing the transfer process into cases in accordance with where theupdate-targeted logical block is located in the track.

Case 1 is a situation in which an update-targeted logical block existsonly in the posterior area of the track (#64 through #115). Case 2 iswhen update-targeted logical blocks exist in both the anterior area (#0through #63) and posterior area of the track. Case 3 is when anupdate-targeted logical block exists only in the anterior area of thetrack.

In this embodiment, gap data 340 is added to the last block in the trackto make the block boundary inside the storage device 210 match thebeginning of the track. Therefore, in Case 1 and Case 2, the existenceof this gap data 340 must be taken into consideration. By contrast,since the update-targeted block exists only in the anterior area of thetrack in Case 3, data can be transferred via alowest-common-multiple-unit data access without taking the gap data 340into account.

FIG. 17 (b) is a schematic diagram showing tables T41 through T43 formanaging the transfer parameters configured in the DMA 122 for eachcase. Table T41 is for managing a transfer parameter for Case 1, TableT42 is for managing a transfer parameter for Case 2, and Table T43 isfor managing a transfer parameter for Case 3. The following explanationwill focus mainly on a situation in which there are 116 blocks per slot.

Table T41 manages the leading LBA of the read target and the number oftransfer blocks in accordance with the number of blocks per slot. TheLBA is the logical block address. When there are 96 blocks per slot, theread-target lead LBA is determined by adding 65 to a value arrived at bymultiplying the slot number by 98. When there are 116 blocks per slot,the read-target lead LBA is determined by adding 65 to a value arrivedat by multiplying the slot number by 118.

When there are 116 extended logical blocks per slot, the number oflogical blocks inside the storage device 210 corresponding to this slotis 118. Then, 65 logical blocks 301 correspond to 64 extended logicalblocks 320.

In Case 1, in which the update-targeted block exists in the posteriorarea of the track, the data must be read out from the beginning of theposterior area. The posterior area begins from logical block #65 andends at logical block #117 inside the storage device. Therefore, thelead LBA of the posterior area of the target track can be determined bymultiplying the slot number by 118 and adding 65.

For example, the lead LBA of the posterior area of the initial track #0is determined as 0×118+65=65. The lead LBA of the posterior area of thesecond track #1 is determined as 1×118+65=183.

In Case 1, the data of the posterior area is transferred from thestorage device 210 to the cache memory 130. Since the size of theposterior area inside the storage device 210 is configured from 53logical blocks 301, 53 is configured as the number of transfer blocks.

In Case 2, in which update-targeted blocks exist in both the anteriorarea and posterior area of the track, the lead LBA of the read target isconfigured as a value arrived at by multiplying the slot number by thenumber of logical blocks configuring this slot. When there are 116extended logical blocks per slot, the lead LBA is determined bymultiplying the slot number by 118. In Case 2, since all the data in thetrack must be transferred to the cache memory 130, the number oftransfer blocks in configured at 118.

In Case 3, in which the update-targeted block exists only in theanterior area of the track, the data of the anterior area is read outfrom the storage device 210 and transferred to the cache memory 130.Therefore, the lead LBA is determined by multiplying the slot number bythe number of logical blocks corresponding to the track. Since only thedata of the anterior area of the track needs to be read out, the numberof transfer blocks is configured to 65.

Thus, in this embodiment, the transfer parameter to be utilized in a DMAtransfer is prepared beforehand on a by-case basis in accordance withthe track update location.

Return to FIG. 16. After determining the case (S54), the DKA 120 issuesa read request to the storage device 210 in accordance with thedetermined case (S55). The DKA 120 specifies the read-target lead LBAand number of transfer blocks, and requests a data-read from the storagedevice 210.

The DKA 120 configures in the DMA 122 a parameter for transferring thedata from the storage device 210 to the buffer memory 122A (S56). TheDKA 120, for example, configures in the DMA 122 adata-transfer-destination address (a buffer memory address) and a numberof transfer bytes. The number of transfer bytes constitutes a valuearrived at by multiplying the number of transfer blocks by 512.

The DKA 120 configures in the DMA 122 a parameter for transferring thedata from the buffer memory 122A to the cache memory 130 (S57). The DKA120, for example, respectively configures in the DMA 122 a buffer memory122A address constituting the transfer source, a cache memory 130address (segment address) constituting the transfer destination, anumber of transfer bytes, and a dirty-bitmap status.

The number of transfer bytes when there are 116 blocks per slot becomes(52×520) bytes for Case 1, (116×520) bytes for Case 2, and (64×520)bytes for Case 3. The number of transfer bytes when there are 96 blocksper slot becomes (32×520) bytes for Case 1, (96×520) bytes for Case 2,and (64×520) bytes for Case 3.

Configuring the number of transfer bytes as described hereinabove,results in the gap data 340 not being transferred from the buffer memory122A to the cache memory 130 as shown in FIG. 11 (2) and FIG. 12 (3).

This is because configuring the dirty-bitmap status in the DMA 122 doesnot allow the scope of data to be updated to be transferred from thebuffer memory 122A to the cache memory 130. That is, the new datareceived from the host 20 is prevented from being overwritten by the olddata read out from the storage device 210. Therefore, the DMA 122 doesnot transfer data from the buffer memory 122A to the cache memory 130for a block that has “1” configured in the dirty-bitmap.

Furthermore, in the case of RAID 5, which will be explained hereinbelow,the old data is also transferred from the buffer memory 122A to thecache memory 130 due to the need to create new parity. Therefore, inRAID 5, there is no need to configure the status of the dirty-bitmap inthe DMA 122.

A DMA transfer is started when the transfer parameter is configured inthe DMA 122 by S56 and S57 (S58). The DKA 120 transitions to standbyuntil the DMA transfer from the buffer memory 122A to the cache memory130 has ended (S59). When the DMA transfer is over (S59: YES), theboundary correction process ends.

FIG. 18 shows the details of the destage process presented in S34 ofFIG. 15. In this destage process, the data is transferred from the cachememory 130 to the storage device 210 by way of the buffer memory 122A.

The DKA 120 checks the number of extended logical blocks configuring oneslot (S70), and determines if there are either 96 or 116 extendedlogical blocks per slot (S71). When the number of blocks per slot isneither 96 nor 116 (S71: NO), the DKA 120 configures a transferparameter in the DMA 122 on the basis of lowest-common-multiple-unitdata access (S72). This is because data can be transferred in alowest-common-multiple unit when there are either 128 blocks or 512blocks per slot (S71: NO).

When there are either 96 or 116 extended logical blocks per slot (S71:YES), the DKA 120 configures a parameter in the DMA 122 for transferringthe data from the cache memory 130 to the buffer memory 122A (S73). TheDKA 120, for example, configures in the DMA 122 a transfer-source cacheaddress, a transfer-destination buffer memory address, and a number oftransfer bytes. The dirty-bitmap status does not have to be configuredin the DMA 122.

The number of transfer bytes when there are 116 blocks per slot becomes(52×520) bytes for Case 1, (116×520) bytes for Case 2, and (64×520)bytes for Case 3. The number of transfer bytes when there are 96 blocksper slot becomes (32×520) bytes for Case 1, (96×520) bytes for Case 2,and (64×520) bytes for Case 3.

The DKA 120 configures a parameter in the DMA 122 for transferring datafrom the buffer memory 122A to the storage device 210 (S74). The DKA 120configures in the DMA 122 a transfer-source buffer memory 122A address,a transfer-destination storage device address, and a number of transferblocks.

The transfer-destination storage device address is configured to thesame value as the read-target lead LBA described used FIG. 17. Thenumber of transfer blocks is also configured to the same value as thenumber of transfer blocks described using FIG. 17 (S74).

Configuring the number of transfer blocks the same is described usingFIG. 17 makes it possible to add gap data 340 at the end of the data,and to write this data to the storage device 210 as shown in FIGS. 13(5) and 13 (6). The gap data 340 can be all 0 bits (0 padding), and itcan be an indefinite value.

This is because the gap data 340 is only used for making the startlocation of the track lead block match the start location of the logicalblock inside the storage device, and is not transferred to the cachememory 130.

The DKA 120, upon completing the configuration to the DMA 122, issues awrite request to the primary disk (the primary storage device 210)(S75). The DKA 120 transitions to standby until the data is transferredfrom the buffer memory 122A to the primary storage device 210 by the DMA122 (S76).

When the data transfer to the primary storage device 210 has ended (S76:YES), the DKA 120 transfers the same data to the secondary storagedevice 210 by repeating steps S70 through S76. When the data transfer tothe secondary storage device 210 has ended (S77: YES), the destageprocess ends.

When destaging the data inside the cache memory 130 to the secondarystorage device 210, there is no need to carry out the processingdescribed in S33 of FIG. 15. This is because the same data isrespectively written to both the primary and secondary storage devices210.

Configuring this embodiment like this makes it possible to store anextended logical block 320 to which a guarantee code 310 has been addedin a storage device 210 having a fixed block size of 512 bytes.

Furthermore, in this embodiment, when the lowest common multiple of thesize of the logical block 301 and the size of the extended logical block320 does not match the track size, which is the host 20 management unit,a write process can be carried out using only data corresponding to thetrack having the update-targeted block, doing away with the need tocarry out a write process that extends across a plurality of adjacenttracks.

Therefore, in this embodiment, there is no need to stand by until acommand process related to the adjacent track has ended. Furthermore, inthis embodiment, it is possible to prevent the increased utilization ofthe cache memory 130, and to curb the degradation of the cache hitratio. Eliminating wait time and preventing a drop in the cache hitratio can prevent the degradation of storage controller 10 throughput.

In this embodiment, since boundary correction is carried out using theDMA 122 and buffer memory 122A inside the DKA 120, processing can becarried out more efficiently than when boundary correction is carriedout in the cache memory 130.

Embodiment 2

A second embodiment of the present invention will be explained based onFIGS. 19 through 22. The following embodiments, to include thisembodiment, correspond to variations of the first embodiment. In thisembodiment, the processing of a plurality of contiguous tracks will beexplained.

FIG. 19 shows how to transfer the data of a plurality of contiguoustracks from the cache memory 130 to the storage device 210. As shown inFIG. 19 (1) (b), gap data 340 is inserted at the end of track #0 in thebuffer memory 122A. Therefore, as shown in FIG. 19 (2) (c), the gap data340 is also written to the logical block 301 of the storage device 210.Consequently, the start location of the lead block of track #1 matchesthe start location of the logical block.

FIG. 20 shows how to transfer data of a plurality of contiguous tracksfrom the storage device 210 to the cache memory 130. As shown in FIG. 20(1), the data of a plurality of tracks is transferred from the storagedevice 210 to the buffer memory 122A. This data comprises gap data 340.

As shown in FIG. 20 (2), data, from which the gap data 340 has beenremoved, is transferred from the buffer memory 122A to the cache memory130. Configuring the transfer-source address and number of transferbytes to a suitable value makes it possible to transfer only the dataitself to the cache memory 130 without transferring the gap data 340 tothe cache memory 130.

FIG. 21 is a flowchart showing a sequential read process. The CHA 110monitors the access pattern of the host 20, and stores the host 20access history in an access history management table T50 (S90). Theaccess history management table T50, for example, manages a host ID;device ID; access time; command type; and number of slots (number oftracks).

The CHA 110 determines whether or not to carry out a prior-read based onaccess pattern learning results (S91). A prior-read is a process forreading data from the storage device 210 and storing this data in thecache memory 130 prior to receiving a request from the host 20. When itis possible to predict that data will be read out sequentially, the CHA110 will decide to execute a prior-read process (S91: YES), and indicateto the DKA 120 to start the prior-read process (S92).

The indication from the CHA 110 to the DKA 120, for example, comprisesthe lead slot number and VDEV number where the read will start.

The DKA 120, upon receiving the indication from the CHA 110 (S100),references the VDEV management table T30 on the basis of the specifiedVDEV number, and detects the table RAID level and disk type (S101).

The DKA 120 determines whether or not the prior-read-targeted storagedevice 210 is an FC disk (S102). When the prior-read-targeted storagedevice 210 is an FC disk (S102: YES), the DKA 120 executes a prior-readprocess for the FC disk (S103). Since the sector length of the FC diskcan be made to match the size of the extended logical block 320 as wasexplained hereinabove, there is no need to correct the data boundaries.

When the prior-read-targeted storage device 210 is not an FC disk (S102:NO), the DKA 120 configures 16 for the number of prior-read-targetedslots (S104), and indicates the start of a read to both the primarystorage device and the secondary storage device (S105). The DKA 120splits the number of prior-read-targeted slots, reads out data fromeight slots in each of the primary and secondary storage devices, andtransfers this data to the cache memory 130 (S106).

FIG. 22 is a flowchart showing the details of the transfer process fromthe disk to the cache memory presented in S106 of FIG. 21. This processis executed for both the primary storage device and the secondarystorage device. That is, the prior-read process is executedsimultaneously for both the primary storage device and the secondarystorage device.

The DKA 120 prepares an SLCB and cache segment 131 for storing theread-targeted data (S110). The DKA 120 issues a read request to thestorage device 210 (S111). This read request comprises aread-start-target LBA and the number of read-out blocks.

The DKA 120 configures a parameter in the DMA 122 for transferring datafrom the storage device 210 to the buffer memory 122A (S112). The DKA120, for example, configures in the DMA 122 the number of bytes to betransferred from the storage device 210 to the buffer memory 122A, andthe transfer-destination buffer address. Consequently, eight slots worthof data is transferred from the storage device 210 to the buffer memory122A.

When there are 116 extended logical blocks per slot, the number oflogical blocks corresponding to each slot is 118. Therefore, (118×8)logical blocks from the logical block specified by the read-start LBAare read out from the storage device 210, and transferred to the buffermemory 122A.

When the data transfer from the storage device 210 to the buffer memory122A is complete (S113: YES), the DKA 120 configures in the DMA 122 aparameter, which is utilized for transferring data from the buffermemory 122A to the cache memory 130 (S114). The DKA 120, for example,configures in the DMA 122 a transfer-source buffer address, number oftransfer bytes, and transfer-destination segment address. Thisconfiguration is carried out for each of eight slots. That is, the datatransfer from the buffer memory 122A to the cache memory 130 is carriedout for each slot.

The DKA 120 stands by until the transfer of one slot worth of data fromthe buffer memory 122A to the cache memory 130 has ended (S115). Whenthe data transfer for one slot has ended (S115: YES), the DKA 120determines whether or not the data transfer has ended for all eightslots (S116).

S114 through S115 are repeatedly executed until the data transfer fromthe buffer memory 122A to the cache memory 130 is complete for eightslots. When the data transfer is complete for eight slots (S116: YES),this processing ends.

Configuring this embodiment in this way also exhibits the same effect asthe first embodiment. In addition, in this embodiment, it is alsopossible to efficiently handle data from a plurality of contiguoustracks.

Embodiment 3

A third embodiment will be explained based on FIGS. 23 and 24. In thisembodiment, the carrying out of a random read process will be explained.FIG. 23 shows a flowchart of the random read process.

The CHA 110, upon receiving a read command from the host 20 (S120),indicates a data-read to the DKA 120 (S121). This indication, forexample, comprises a slot number, VDEV number, read-targeted lead blocknumber, and number of blocks.

The DKA 120, upon receiving the indication from the CHA 110 (S130),acquires a RAID level and disk type from the VDEV management table T30on the basis of the VDEV number (S131).

The DKA 120 determines whether or not the disk type is an FC disk(S132), and when it is determined that the disk type is an FC disk(S132: YES), executes an FC disk read process (S133).

When the read-target storage device 210 is a disk other than an FC disk(S132: NO), the DKA 120 specifies the read-target storage device 210(S134), and prepares an SLCB and cache segment 131 for storing theread-data (S135). Then, the DKA 120 executes a data transfer from thestorage device 210 to the cache memory 130 (S135).

FIG. 24 is a flowchart of processing for carrying out the data transferfrom the storage device 210 to the cache memory 130 presented as S136 inFIG. 23. The DKA 120 determines if the number of blocks per slot iseither 96 blocks or 116 blocks (S140).

When the number of blocks per slot is neither 96 blocks nor 116 blocks(S140: NO), the DKA 120 transfers data from the storage device 210 tothe cache memory 130 in accordance with a lowest-common-multiple-unitdata access (S141).

When the number of blocks per slot is either 96 blocks or 116 blocks(S140: YES), the DKA 120 determines based on the dirty-bitmap statusinside the SLCB if any of the above-described Case 1 through Case 3pertain (S142). That is, the DKA 120 determines the case for decidingthe number of transfer bytes in accordance with the track location ofthe read-targeted block.

The DKA 120 issues a read request to the storage device 210 inaccordance with the determined case (S143). The DKA 120 configures aparameter in the DMA 122 for transferring data from the storage device210 to the buffer memory 122A (S144). For example, the DKA 120configures in the DMA 122 a read-target address, a transfer-destinationbuffer address, and number of transfer bytes. Consequently, a DMAtransfer from the storage device 210 to the buffer memory 122A isstarted.

The DKA 120 stands by until the data transfer from the storage device210 to the buffer memory 122A has ended (S145). When the transfer hasended (S145: YES), the DKA 120 configures a parameter in the DMA 122 fortransferring the data from the buffer memory 122A to the cache memory130 (S146). For example, the DKA 120 respectively configures in the DMA122 a transfer-source buffer address, a transfer-destination segmentaddress, and a number of transfer bytes. Consequently, a data transferfrom the buffer memory 122A to the cache memory 130 is started.Furthermore, as was described hereinabove, the gap data 340, which wasread out from the storage device 210, is not transferred to the cachememory 130.

When the data transfer from the buffer memory 122A to the cache memory130 is complete (S147: YES), the DKA 120 notifies the CHA 110 to theeffect that the processing of the read request has ended (S148). Uponreceiving this notification, the CHA 110 sends the data, which has beentransferred to the cache memory 130, to the host 20.

Furthermore, the guarantee code 310 is removed from the data sent to thehost 20. Configuring this embodiment in this way also exhibits the sameeffects as the first embodiment.

Embodiment 4

A fourth embodiment will be explained based on FIG. 25. In thisembodiment, the application of the present invention to RAID 5 will beexplained. The respective embodiments described hereinabove wereexplained primarily in terms of RAID 1. However, the present inventionis not limited to RAID 1, and can also be applied to other RAID levels,to include RAID 5.

FIG. 25 is a schematic diagram showing how to transfer data from thebuffer memory 122A to the cache memory 130 in a RAID 5. For RAID 5, aread page and a write page are prepared in the cache memory 130. Theread page is a cache area for storing data read out from the storagedevice 210. The write page is a cache area for storing data receivedfrom the host 20.

In RAID 5, a new parity is computed on the basis of new data receivedfrom the host 20, and old data and old parity read out from the storagedevice 210. Therefore, unlike in a RAID 1, all the old data read out tothe buffer memory 122A is transferred to the read page.

Since parity is used in RAID 5, RAID 5 differs from RAID 1 in thatparity is created and transferred. However, the process for reading outold parity from the storage device 210 by way of the buffer memory 122A,and the process for writing new parity to the storage device 210 by wayof the buffer memory 122A can be carried out the same as for data.

On the basis of the content disclosed in this specification and thefigures, it should be possible for a so-called person having ordinaryskill in the art to easily comprehend the fact that the presentinvention is also applicable to other RAID levels, such as RAID 6.

Embodiment 5

A fifth embodiment will be explained based on FIG. 26. In thisembodiment, the boundary correction process is carried out in thestorage device 210. FIG. 26 is a block diagram showing the essentialparts of a storage controller according to this embodiment.

In this embodiment, the buffer memory and boundary correction programare removed from the DMA 122 of the DKA 120. Further, the protocol chip121A is configured as a dedicated FC disk protocol chip.

A plurality of storage devices 210A through 210C of different disk typesis connected to the protocol chip 121A. For example, storage device 210Ais a SATA disk, storage device 210B is a SAS disk, and storage device210C is an FC disk.

Storage device 210C, which is an FC disk, is connected as-is to theprotocol chip 121A. By contrast, the storage devices 210A, 210B, whichare not FC disks, are connected to the protocol chip 121A by way ofrespective conversion circuits 400. The respective conversion circuits400 of storage device 210A and storage device 210B, for example, eachcomprise a buffer memory 401 and a boundary correction unit 402. Theseconversion circuits 400 are connected to control circuits inside thestorage devices 210.

The buffer memory 401 temporarily stores data to be transferred to thestorage device 210 from the DKA 120, and data to be transferred to theDKA 120 from the storage device 210. The boundary correction unit 402 isfor carrying out a boundary correction process when transferring datafrom the storage device 210 to the DKA 120, and for carrying out aboundary correction process when transferring data from the DKA 120 tothe storage device 210. Since the respective boundary correctionprocesses were described in the first embodiment, explanations of theseprocesses will be omitted here.

The DKA 120 can treat all the storage devices 210 under its control asFC disks. The DKA 120 issues a read command or a write command to thestorage device 210 using a 520-byte extended logical block 320 as theunit the same as an indication to the FC disk. There is no need to carryout boundary correction inside the DKA 120. The boundary correctionprocess is carried out by the conversion circuit 400.

Configuring this embodiment in this way also exhibits the same effectsas the first embodiment. Furthermore, since boundary correction iscarried out by the conversion circuit 400 disposed in the storage device210 in this embodiment, the processing of the DKA 120 can be simplified.Further, since a SATA disk and SAS disk can be treated as FC disks, anexisting storage device 210 can be utilized effectively.

Furthermore, the present invention is not limited to the above-describedembodiments. A person having ordinary skill in the art will be able tomake various additions and changes without departing from the scope ofthe present invention. A person having ordinary skill in the art willalso be able to suitably combine the above-mentioned respectiveembodiments. For example, in the fifth embodiment, three types ofstorage devices are presented, but, instead of this, the presentinvention can also be configured using only SATA disks or only SASdisks.

1. A storage controller for controlling data input/output between a hostcomputer and a storage device storing data, comprising: a firstcommunication controller, which sends/receives data to/from said hostcomputer, and which sends/receives the data to/from said host computerin first block units having a first size; a first data adder forcreating a second block having a second size that is larger than saidfirst size by respectively adding a prescribed first data to each ofsaid first blocks of data received from said host computer; a secondcommunication controller for sending/receiving data to/from said storagedevice which stores the data in said first block units; a first memory,which is provided between said first communication controller and saidsecond communication controller, and which manages the data in saidsecond block units; a second memory, which is provided between saidfirst memory and said storage device; and a boundary correction unit,which matches a boundary of a track that is a unit of data managementused by said host computer, to the boundary of said first block insidesaid storage device, and which (1) matches said boundary of a track tosaid boundary of a first block inside said storage device by adding aprescribed-size second data to data to be transferred from said firstmemory to said second memory, and (2) matches said boundary of a trackto said boundary of a second block inside said first memory by removingsaid second data from the data to be transferred from said second memoryto said first memory.
 2. The storage controller according to claim 1,wherein said boundary correction unit matches the start position of thelead second block of said respective second blocks, which configure thedata to be transferred from said first memory to said second memory, tothe start position of said first block inside said storage device. 3.The storage controller according to claim 1, wherein said boundarycorrection unit, by adding said second data to the data to betransferred from said first memory to said second memory, makes thisdata into data that is an integral multiple of said first size.
 4. Thestorage controller according to claim 1, wherein said second data iseither padding data configured from a 0 bit, or indefinite data.
 5. Thestorage controller according to claim 1, wherein said boundarycorrection unit decides a scope of the data to be read out from saidstorage device to said second memory in accordance with a location, onsaid track, of said second block to be updated by said host computer. 6.The storage controller according to claim 1, wherein said boundarycorrection unit determines whether said location, on the track, of saidblock to be updated by said host computer corresponds to any of: (C1) afirst case in which said location on the track is only in a posteriorarea of the track, which is subsequent to an anterior area of the trackfrom the beginning of said track to a data size determined as the lowestcommon multiple of said first size and said second size; (C2) a secondcase in which said location on the track is in both said track anteriorarea and said track posterior area; (C3) a third case in which saidlocation on the track is only in said track anterior area, and decides asize of data transfer between said second memory and said storage devicein accordance with the determined case.
 7. The storage controlleraccording to claim 1, wherein said boundary correction unit and saidsecond memory are respectively disposed in said second communicationcontroller.
 8. The storage controller according to claim 1, wherein saidboundary correction unit and said second memory are respectivelydisposed in said storage device.
 9. A method for controlling a storagecontroller, which controls data input/output between a host computer anda storage device, said method comprising the steps of: receiving, fromsaid host computer, update-targeted data in first block units having afirst size; respectively adding a prescribed first data to each of saidfirst blocks of said update-targeted data, and creating a second blockhaving a second size that is larger than said first size; storing, in afirst memory, update-targeted data, which has been converted to data insaid second block units; reading out from said storage device prescribeddata of a prescribed scope comprising said update-targeted data, andstoring this data in a second memory; removing a second data from saidprescribed data stored in said second memory, converting said prescribeddata to data of an integral multiple of said second size, andtransferring this converted data to said first memory; merging in saidfirst memory said prescribed data transferred to said first memory withsaid update-targeted data stored in said first memory, and creatingmerged data; transferring said merged data to said second memory;converting in said second memory said merged data to data of theintegral multiple of said first size by adding a prescribed size seconddata at the end of said merged data; and writing said converted mergeddata to said storage device.
 10. The method for controlling a storagecontroller according to claim 9, wherein (C1) in a first case where alocation, on a track, of said update-targeted data is only in a trackposterior area, which is subsequent to a track anterior area from thebeginning of the track to a data size determined as the lowest commonmultiple of said first size and said second size, the data of said trackposterior area is read out from said storage device as the data of saidprescribed scope; (C2) in a second case where the location, on thetrack, of said update-targeted data is in both said track anterior areaand said track posterior area, the entirety of said track is read outfrom said storage device as the data of said prescribed scope; and (C3)in a third case where the location, on the track, of saidupdate-targeted data is only in said anterior area, and the data of saidtrack anterior area is read out from said storage device as the data ofsaid prescribed scope.